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january 2010 doc id 15698 rev 2 1/47 47 L6706 vr11.1 single phase controller with integrated driver features 8-bit programmable output up to 1.60000 v - intel ? vr11.1 dac high current embedded driver high output voltage accuracy programmable droop function imon output load transient boost ltb technology? to minimize the number of output capacitors full differential current sense across inductor differential remote voltage sensing adjustable voltage offset lsless startup to manage pre-biased output feedback disconnection protection preliminary overvoltage protection programmable overcurrent protection programmable overvoltage protection adjustable switching frequency ssend and outen signal vfqfpn-40 6x6 mm package with exp. pad applications vtt and vaxg rails cpu power supply high density dc/dc converters description the device implements a single phase step-down controller with inte grated high current driver in a compact 6x6 mm body package with exposed pad. the device embeds vr11.x dacs: the output voltage ranges up to 1.60000 v managing d-vid with high output voltage accuracy over line and temperature variations. imon capability guarante e full compatibility with vr11.1 enabling additional power saving technique. programmable droop function allows to supply all the latest intel cpu rails. load transient boost ltb technology? reduces system cost by providing the fastest response to load transition. the controller assures fast protection against load over current and under / over voltage. feedback disconnection prevents from damaging the load in case of disconnections in the system board. in case of over-current , the system works in constant current mode until uvp. vfqfpn-40 6 x 6 mm table 1. device summary order codes package packing L6706 vfqfpn-40 tr ay L6706tr tape and reel www.st.com
contents L6706 2/47 doc id 15698 rev 2 contents 1 principle application circuit and block diagra m . . . . . . . . . . . . . . . . . . . 4 1.1 principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 voltage identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 dac and current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1 offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2 droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 droop thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 output current monitoring (imo n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11 load transient boost technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 dynamic vid transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13 enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
L6706 contents doc id 15698 rev 2 3/47 14.1 low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15 output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 34 15.1 undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15.2 preliminary overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15.3 over voltage and programmable ovp . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15.4 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15.5 feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 17 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18 system control loop compensati on . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 20 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 20.1 power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 20.2 small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 43 20.3 embedding L6706 - based vr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 21 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 22 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
principle application circuit and block diagram L6706 4/47 doc id 15698 rev 2 1 principle application circuit and block diagram 1.1 principle application circuit figure 1. principle application circuit (a) a. refer to the application note for the reference schematic. l1 40 39 38 boot ugate phase lgate 36 cs- 18 cs+ 17 rg hs1 ls1 ssend 29 c out vcc_core load vid4 25 vid3 24 vid2 23 vid1 22 vid0 21 vid5 26 sgnd 2 l in v in = 12v c in L6706 r c 27 vid6 vid7 outen 16 vid bus from cpu imon 9 ss_end v in r f c f c p r ltb c ltb 20 L6706 ref.sch ci mon r out vcc 3 vccdr 35 gnd in 5v sb optional:pre-ovp v cc ovpsel 12 ocset 13 osc/fault 14 ltbgain 10 r ltbgain r ocset r ovp r osc_sgnd r ss_flim ssosc/flimit 15 offset 11 r offset gnd_core r fb1 r fb2 r fb3 ntc r fb to enable circuitry 1k vtt r 1 r 2 r 3 ntc r imon_os +3v3 r imon_tot 220nf expad r osc_vcc to vcc r flimt 10k r ssosc d q optional: see ds 41 ltb r i c i comp fb vsen fbg 8 4 5 6 7 +3v3 int1 int3 31 19 pgnd 37 dgnd 1 int2 28 int4 33 +12v optional: see ds optional: see ds
L6706 principle application circuit and block diagram doc id 15698 rev 2 5/47 1.2 block diagram figure 2. block diagram logic pwm adaptive anti cross conduction boot ugate phase lgate pgnd oscillator ch current reading L6706 control logic and protections pwm vcc digital soft start dac with dynamic vid control cs- cs+ 20ua outen osc / fault vid0 vid1 vid2 vid3 vid4 vid5 vid6 fb vsen ovp comparator +175mv 1.800v / ovp error amplifier gnd drop recovery delivered current ovpsel ssosc/ flimt vid7 comp fbg i droop vref lt b 50ua i ocset +.1240v pwm1 outen +.1240v i offset i offset offset +.1240v ltbgain vccdr 10ua ocset ovp vcc sgnd vccdr outen ssosc ssend i droop imon ocset info info lt b lt b int1 int2 int3 int4 int1 int2 int3 int4 dgnd
pins description and connection diagrams L6706 6/47 doc id 15698 rev 2 2 pins description and connection diagrams figure 3. pins connection (top view) 2.1 pin description 37 36 35 34 33 32 31 30 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 123456789 offset ovpsel ocset osc/fault ssosc/flimit outen cs+ cs- int1 boot ugate phase pgnd L6706 vccdr n.c. int4 n.c. int2 vid7 vid6 vid5 vid4 vid3 vid2 vid1 sgnd vcc comp fb vsen fbg lt b imon ltbgain ssend lgate dgnd 19 vid0 28 n.c. 29 int3 20 40 39 38 table 2. pin description n name description 1dgnd digital gnd. it must be connected to pgnd (power ground). 2sgnd all the internal references are referred to this pin. connect it to the pcb signal ground. 3vcc device supply voltage pin. the operative supply voltage is 12 v 1 5%. filter with 1 x 1 f mlcc capacitor vs. sgnd. 4comp error amplifier output. connect with an r f - c f //c p vs. fb pin. the device cannot be disabled by pulling down this pin. 5fb error amplifier inverting input pin. connect with a resistor r fb vs. vsen and with an r f - c f //c p vs. comp pin. a current proportional to the load current is sourced from this pin in order to implement the droop effect. see ?droop function? section for details. 6 vsen output voltage monitor, manages ovp/uvp protections and fb disconnection. connect to the positive side of the load to perform remote sense. see ?layout guidelines? section for proper layout of this connection. 7fbg connect to the negative side of the load to perform remote sense. see ?layout guidelines? section for proper layout of this connection.
L6706 pins description and connection diagrams doc id 15698 rev 2 7/47 8ltb load transient boost pin. internally fixed at 2 v, connecting a r lt b - c lt b vs. v out allows to enable the load transient boost technology?: as soon as the device detects a transient load it turns on the phase. short to sgnd to disable the function. see ?load transient boost technology? section for details. 9imon current monitor output pin. a current proportional to the load current is sourced from this pin. connect through a resistor r mon to sgnd (or fbg) to implement a load indicator. the pin voltage is clamped to 1.1 v max. 10 ltbgain load transient boost technology? gain pin. internally fixed at 1.24 v, connecting a r ltbgain resistor vs sgnd allows setting the gain of the ltb action. see see ?load transient boost technology? section for details. 11 offset offset programming pin. internally fixed at 1.240 v, connecting a r offset resistor vs. sgnd allows setting a current that is mirrored into fb pi n in order to program a positive offset according to the selected r fb . short to sgnd to disable the function. see ?offset (optional)? section for details. 12 ovpsel over voltage programming pin. internally pulled up by 20 a (min) to 3.3 v. leave floating to use built-in protection thresholds (ovp th = vid + 175 mv typ). connect to sgnd through a r ovp resistor and filter with 100 pf (max) to set the ovp threshold to a fixed voltage according to the r ovp resistor. see ?over voltage and programmable ovp? section for details. 13 ocset over current setting, psi action pin. connect to sgnd through a r ocset resistor to set the ocp threshold. see ?overcurrent protection? section for details. 14 osc/ fault oscillator, fault pin. it allows programming the switching frequency f sw . frequency is programmed according to the resistor connected fr om the pin vs. sgnd or vcc with a gain of 9.1 khz/a (see relevant section fo r details). leaving the pin floating programs a switching frequency of 200 khz. the pin is forced high (3.3 v typ) to signal an ovp/uvp fault: to recover from this condition, cycle vcc or the outen pin. see ?oscillator? section for details. 15 ssosc/ flimit soft-start oscillator pin. by connecting a resistor r ss to gnd, it allows programming the soft-start time. soft-start time t ss will proportionally change with a gain of 25 [s / k ]. the same slope implemented to reach v boot has to be considered also when the reference moves from v boot to the programmed vid co de. the pin is kept to a fixed 1.240 v. see ?soft-start? section for details. it also allows to select maximum ltb frequency. see ?load transient boost technology? section for details. table 2. pin description (continued) n name description
pins description and connection diagrams L6706 8/47 doc id 15698 rev 2 16 outen output enable pin. internally pulled up by 10 a (typ) to 3 v. forced low, the device stops operations with all mosfets off: all t he protections are disabled except for preliminary over voltage. leave floating, the device starts-up implementing soft- start up to the selected vid code. cycle this pin to recover latch from protections; filter with 1 nf (typ) vs. sgnd. 17 cs+ current sense positive input. connect through an r-c filter to the phase-side of the output inductor. see section 20: layout guidelines on page 43 for proper layout of this connection. 18 cs- current sense negative input. connect through a rg resistor to the output-side of the output inductor. see section 20: layout guidelines on page 43 for proper layout of this connection. 19 int1 test mode pin. it must be left unconnected or connected to 3.3 v. 20 to 27 vid0 to vid7 voltage identification pins. (not internally pulled up). connect to sgnd to program a '0' or connect to the external pull-up resistor to program a '1'. they allow programming output voltage as specified in ta bl e 7 . 28 int2 test mode pin. it must be connected to sgnd. 29 ssend soft-start end signal. open drain output sets free after ss has finished and pulled low when triggering any protection. pull up to a volt age lower than 3.3 v, if not used it can be left floating. 30 n.c. not internally connected. 31 int3 test mode pin. it must be connected to 12 v. 32 n.c. not internally connected. 33 int4 test mode pin. it must be connected to 12 v. 34 n.c. not internally connected. 35 vccdr ls driver supply. vcddr pin voltage has to be the same of vcc pin. filter with 1 x 1 f ml cc capacitor vs. pgnd. 36 lgate ls driver output. a small series resistor helps in reducing device-dissipated power. 37 pgnd power ground pin (ls drivers return path). connect to power ground plane. 38 phase hs driver return path. it must be connected to the hs mosfet source and provides return path for the hs driver. table 2. pin description (continued) n name description
L6706 pins description and connection diagrams doc id 15698 rev 2 9/47 2.2 thermal data table 3. thermal data 39 ugate hs driver output. it must be connected to the hs mosfet gate. a small series resistors helps in reducing device-dissipated power. 40 boot hs driver supply. connect through a capacitor (100 nf typ.) to phase and provide necessary bootstrap diode. a small resistor in series to the boot diode helps in reducing boot capacitor overcharge. pa d thermal pa d exposed pad connects the silicon substrate. as a consequence it makes a good thermal contact with the pcb to dissipate the power necessary to drive the external mosfets. connect it to the power ground plane us ing 4.3 x 4.3 mm square area on the pcb and with nine vias, to improve thermal conductivity. table 2. pin description (continued) n name description symbol parameter value unit r thja thermal resistance junction to ambient (device soldered on 2s2p pc board) 35 c / w r thjc thermal resistance junc tion to case 1 c / w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range -10 to 125 c
electrical specifications L6706 10/47 doc id 15698 rev 2 3 electrical specifications 3.1 absolute maximum ratings table 4. absolute maximum ratings symbol parameter value unit v cc, v ccdr to p g n d 1 5 v v boot - v phase boot voltage 15 v v ugate - v phase 15 v lgate to pgnd -0.3 to vcc+0.3 v all other pins to pgnd -0.3 to 3.6 v v phase negative peak voltage to pgnd; t < 400 ns vcc = vccdr = 12 v -8 v positive voltage to pgnd vcc = vccdr = 12 v 26 v positive peak voltage to pgnd; t < 200 ns vcc = vccdr = 12 v 30 v maximum withstanding voltage range test condition: cdf-aec-q100-002- ?human body model? acceptance criteria: ?normal performance? +/- 1750 v
L6706 electrical specifications doc id 15698 rev 2 11/47 3.2 electrical characteristics v cc = 12 v 15%, t j = 0 c to 70 c unless otherwise specified table 5. electrical characteristics symbol parameter test cond itions min. typ. max. unit supply current and power-on i cc vcc supply current ugate and lgate open; vcc = vboot = 12 v 23 27 ma i ccdr vccdr supply current lgate = open, vccdr = 12 v 5 7 ma i boot boot supply current ugate = open, phase to pgnd; vcc = boot = 12 v 23ma power-on uvlo vcc vcc turn-on vcc rising; vccdr = vcc 3.7 4.0 v vcc turn-off vcc falling; vccdr = vcc 3.3 3.5 v oscillator and inhibit f osc initial accuracy osc = open osc = open; t j = 0 to 125 c 180 175 200 200 220 225 khz khz td 1 ss delay time 1 1.5 ms td 2 ss td 2 time r ssosc = 20 k 500 s td 3 ss td 3 time 50 200 s outen output enable rising thresholds voltage 0.80 0.85 0.90 v hysteresis 100 mv output pull-up current outen to sgnd 10 a vosc ramp amplitude 1.5 v fault voltage at pin osc/fault ovp and uvp active 3.3 v reference and dac k vid output voltage accuracy vid = 1.000 v to vid = 1.600 v fb = vout; fbg = gndout -0.5 - 0.5 % vid = 0.800 v to vid = 1.000 v fb = vout; fbg = gndout -5 - +5 mv vid = 0.500 v to vid = 0.800 v fb = vout; fbg = gndout -8 - +8 mv v boot boot voltage 1.081 v vid ih vid thresholds input low 0.35 v vid il input high 0.8 v error amplifier a 0 ea dc gain 130 db
electrical specifications L6706 12/47 doc id 15698 rev 2 sr ea slew-rate comp = 10 pf to sgnd 25 v/ s differential curren t sensing and offset v ocset ocset pin voltage 1.120 1.260 1.400 mv k idroop droop current deviation from nominal value rg = 1 k ; i droop = 25 a; -2 - +2 a k ioffset offset current accuracy i offset = 50 a to 250 a-5-5% i offset offset current range 0 250 a v offset offset pin bias i offset = 0 to 250 a1.240v gate drivers t rise ugate high side rise time boot-phase = 12 v; c ugate to phase = 3.3 nf 20 ns i ugate high side source current boot-phase = 12 v 1.5 a r ugate high side sink resist ance boot-phase = 12 v 1.8 t rise lgate low side rise time vccdr = 12 v; c lgate to pgnd = 5.6 nf 25 ns i lgate low side source current vccdr = 12 v 2 a r lgate low side sink resistance vccdr = 12 v 1.2 protections ovp over voltage protection (vsen rising) before v boot 1.24 1.300 v above vid (after td 3 ) 150 175 200 mv programmable ovp i ovp current ovp = sgnd 20 22 24 a comparator offset voltage ovp = 1.800 v -20 0 20 mv pre-ovp preliminary over voltage protection uvlo ovp < vcc < uvlo vcc vcc> uvlo vcc and outen = sgnd vsen rising 1.750 1.800 1.850 v hysteresis 350 mv uvp under voltage threshold vsen falling; below vid 550 600 650 mv v ssend ss_end voltage low i = -4 ma 0.4 v table 5. electrical characteristics (continued) symbol parameter test cond itions min. typ. max. unit
L6706 voltage identifications doc id 15698 rev 2 13/47 4 voltage identifications table 6. voltage identification (vid) mapping intel vr11.x vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 800 mv 400 mv 200 mv 100 mv 50 mv 25 mv 12.5 mv 6.25 mv table 7. voltage identification (vid) intel vr11.x (1) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 ) 0 0 off 4 0 1.21250 8 0 0.81250 c 0 0.41250 0 1 off 4 1 1.20625 8 1 0.80625 c 1 0.40625 0 2 1.60000 4 2 1.20000 8 2 0.80000 c 2 0.40000 0 3 1.59375 4 3 1.19375 8 3 0.79375 c 3 0.39375 0 4 1.58750 4 4 1.18750 8 4 0.78750 c 4 0.38750 0 5 1.58125 4 5 1.18125 8 5 0.78125 c 5 0.38125 0 6 1.57500 4 6 1.17500 8 6 0.77500 c 6 0.37500 0 7 1.56875 4 7 1.16875 8 7 0.76875 c 7 0.36875 0 8 1.56250 4 8 1.16250 8 8 0.76250 c 8 0.36250 0 9 1.55625 4 9 1.15625 8 9 0.75625 c 9 0.35625 0 a 1.55000 4 a 1.15000 8 a 0.75000 c a 0.35000 0 b 1.54375 4 b 1.14375 8 b 0.74375 c b 0.34375 0 c 1.53750 4 c 1.13750 8 c 0.73750 c c 0.33750 0 d 1.53125 4 d 1.13125 8 d 0.73125 c d 0.33125 0 e 1.52500 4 e 1.12500 8 e 0.72500 c e 0.32500 0 f 1.51875 4 f 1.11875 8 f 0.71875 c f 0.31875 1 0 1.51250 5 0 1.11250 9 0 0.71250 d 0 0.31250 1 1 1.50625 5 1 1.10625 9 1 0.70625 d 1 0.30625 1 2 1.50000 5 2 1.10000 9 2 0.70000 d 2 0.30000 1 3 1.49375 5 3 1.09375 9 3 0.69375 d 3 0.29375 1 4 1.48750 5 4 1.08750 9 4 0.68750 d 4 0.28750 1 5 1.48125 5 5 1.08125 9 5 0.68125 d 5 0.28125 1 6 1.47500 5 6 1.07500 9 6 0.67500 d 6 0.27500 1 7 1.46875 5 7 1.06875 9 7 0.66875 d 7 0.26875 1 8 1.46250 5 8 1.06250 9 8 0.66250 d 8 0.26250 1 9 1.45625 5 9 1.05625 9 9 0.65625 d 9 0.25625
voltage identifications L6706 14/47 doc id 15698 rev 2 1 a 1.45000 5 a 1.05000 9 a 0.65000 d a 0.25000 1 b 1.44375 5 b 1.04375 9 b 0.64375 d b 0.24375 1 c 1.43750 5 c 1.03750 9 c 0.63750 d c 0.23750 1 d 1.43125 5 d 1.03125 9 d 0.63125 d d 0.23125 1 e 1.42500 5 e 1.02500 9 e 0.62500 d e 0.22500 1 f 1.41875 5 f 1.01875 9 f 0.61875 d f 0.21875 2 0 1.41250 6 0 1.01250 a 0 0.61250 e 0 0.21250 2 1 1.40625 6 1 1.00625 a 1 0.60625 e 1 0.20625 2 2 1.40000 6 2 1.00000 a 2 0.60000 e 2 0.20000 2 3 1.39375 6 3 0.99375 a 3 0.59375 e 3 0.19375 2 4 1.38750 6 4 0.98750 a 4 0.58750 e 4 0.18750 2 5 1.38125 6 5 0.98125 a 5 0.58125 e 5 0.18125 2 6 1.37500 6 6 0.97500 a 6 0.57500 e 6 0.17500 2 7 1.36875 6 7 0.96875 a 7 0.56875 e 7 0.16875 2 8 1.36250 6 8 0.96250 a 8 0.56250 e 8 0.16250 2 9 1.35625 6 9 0.95625 a 9 0.55625 e 9 0.15625 2 a 1.35000 6 a 0.95000 a a 0.55000 e a 0.15000 2 b 1.34375 6 b 0.94375 a b 0.54375 e b 0.14375 2 c 1.33750 6 c 0.93750 a c 0.53750 e c 0.13750 2 d 1.33125 6 d 0.93125 a d 0.53125 e d 0.13125 2 e 1.32500 6 e 0.92500 a e 0.52500 e e 0.12500 2 f 1.31875 6 f 0.91875 a f 0.51875 e f 0.11875 3 0 1.31250 7 0 0.91250 b 0 0.51250 f 0 0.11250 3 1 1.30625 7 1 0.90625 b 1 0.50625 f 1 0.10625 3 2 1.30000 7 2 0.90000 b 2 0.50000 f 2 0.10000 3 3 1.29375 7 3 0.89375 b 3 0.49375 f 3 0.09375 3 4 1.28750 7 4 0.88750 b 4 0.48750 f 4 0.08750 3 5 1.28125 7 5 0.88125 b 5 0.48125 f 5 0.08125 3 6 1.27500 7 6 0.87500 b 6 0.47500 f 6 0.07500 3 7 1.26875 7 7 0.86875 b 7 0.46875 f 7 0.06875 3 8 1.26250 7 8 0.86250 b 8 0.46250 f 8 0.06250 3 9 1.25625 7 9 0.85625 b 9 0.45625 f 9 0.05625 3 a 1.25000 7 a 0.85000 b a 0.45000 f a 0.05000 3 b 1.24375 7 b 0.84375 b b 0.44375 f b 0.04375 table 7. voltage identification (vid) intel vr11.x (1) (continued) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 )
L6706 voltage identifications doc id 15698 rev 2 15/47 3 c 1.23750 7 c 0.83750 b c 0.43750 f c 0.03750 3 d 1.23125 7 d 0.83125 b d 0.43125 f d 0.03125 3 e 1.22500 7 e 0.82500 b e 0.42500 f e off 3 f 1.21875 7 f 0.81875 b f 0.41875 f f off 1. according to intel specs, the device automatically regulates output voltage 19 mv lower to avoid any external offset to modify the built -in 0.5% accuracy improving tob per formances. output regulated voltage is than what extracted from the table lowered by 19 mv. table 7. voltage identification (vid) intel vr11.x (1) (continued) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 )
device description L6706 16/47 doc id 15698 rev 2 5 device description L6706 is single phase pwm controller with embedded high current drivers providing complete control logic and protections for a high performance step-down dc-dc voltage regulator optimized for advanced microprocessor power supply. L6706 is a dual-edge asynchronous pwm controller featuring load transient boost ltb technology?: the device turns on the phase as soon as a load transient is detected allowing to minimize system cost by providing the fastest response to load transition. load transition is detected (through ltb pin) measuring the derivate dv/dt of the output voltage and the dv/dt can be easily programmed extend ing the system design flexibility. moreover, load transient boost (ltb) technology? gain can be easily modified in order to keep under control the output voltage ring back. ltb technology? can be disabled and in this condition the device works as a dual-edge asynchronous pwm. L6706 permits easy system design by allowing current reading across inductor in fully differential mode. also a sense resistor in series to the inductor can be considered to improve reading precision. the controller allows compat ibility with both intel vr11.0 and vr11.1 processors specifications, also performing d-vid transitions accordingly. the device is vr11.1 compatible implementing imon signal. low-side-less startup allows soft-start over pre-biased output avoiding dangerous current return through the main inductor as well as negative spike at the load side. L6706 provides a programmable over-voltage protection to protect the load from dangerous over stress, latching immediately by turning on the lower driver and driving high the osc/fault pin. furthermore, preliminary ovp protection also allows the device to protect load from dangerous ovp when vcc is not above the uvlo threshold or outen is low. the overcurrent protection is externally adjustable through a single resistor. the device keeps constant the peak of the inductor curren t ripple working in constant current mode until the latched uvp. a compact 6 x 6 mm body vfqfpn-40 package with exposed thermal pad allows dissipating the power to drive the external mosfet through the system board.
L6706 dac and current reading doc id 15698 rev 2 17/47 6 dac and current reading L6706 embeds vrd11.x dac (see ta b l e 7 ) that allows to regulate the output voltage with a tolerance of 0.5% recovering from offsets and manufacturing variations. the device automatically introduces a -19 mv (both vrd11.x) offset to the regulated voltage in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a consequence, the calculated system tob. output voltage is programmed through the vid pins: they are inputs of an internal dac that is realized by means of a series of resistors providing a partition of the internal voltage reference. the vid code drives a multiplexer that selects a voltage on a precise point of the divider. the dac output is delivered to an amplifier obtaining the voltage reference (i.e. the set-point of the error amplifier, v ref ). L6706 embeds a flexible, fully-dif ferential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the inductor element. the fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy. reading current across the inductor dcr, the current flowing trough phase is read using the voltage drop across the output inductor or across a sense resistor in it s series and internally converted into a current. the trans-conductance ratio is issued by the external resistor rg placed outside the chip between cs- pin toward the reading points. the current sense circuit always tracks the current information, no bias current is sourced from the cs+ pin: this pin is used as a refere nce keeping the cs- pin to this voltage. to correctly reproduce the inductor current an r-c filtering network must be introduced in parallel to the sensing element. the current that flows from the cs- pin is then given by the following equation (see figure 4 ): where i phase is the current carried by the relative phase. figure 4. current reading connections considering now to match the time constant between the inductor and the r-c filter applied (time constant mismatches caus e the introduction of poles into the current reading network i cs- dcr rg ------------- 1sldcr () ? ? + 1src ?? + ------------------------------------------ - i ? phase ? = l cs+ cs- phase dcr r c rg i phasex inductor dcr current sense i cs- =i info no bias
dac and current reading L6706 18/47 doc id 15698 rev 2 causing instability. in addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance), it results: where i info is the current informatio n reproduced internally. the rg trans-conductance resistor has to be selected using the following formula, in order to guarantee the correct functionality of internal current reading circuitry: where i out max is the maximum output current, dcr max the maximum inductor dcr. l dcr ------------- rc i cs- dcr rg ------------- i phase ? = ? ? i info i info dcr rg ------------- i phase ? = ? == rg dcr max 20 a ------------------------ i out max ? =
L6706 differential remote voltage sensing doc id 15698 rev 2 19/47 7 differential remote voltage sensing the output voltage is sensed in fully-differential mode between the fb and fbg pin. the fb pin has to be connected through a resistor to the regulation point while the fbg pin has to be connected directly to the remote sense ground point. in this way, the output voltage programmed is regulated between the remote sense point compensating motherboard or connector losses. keeping the fb and fbg traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. figure 5. differential remote voltage sensing connections comp to gnd_core (remote sense) error amplifier fb fbg r f c f vsen i droop to vcc_core (remote sense) r fb v prog v ref fbg gnd drop recovery c p i offset
voltage positioning L6706 20/47 doc id 15698 rev 2 8 voltage positioning output voltage positioning is performed by selecting the internal reference value through vid pins and by programming the droop function and offset to the reference (see figure 6 on page 20 ). the currents sourced/sunk from fb pin cause the output voltage to vary according to the external r fb . the output voltage is then driv en by the following relationship: where: offset function can be disabled shorting to sgnd the offset pin. figure 6. voltage positioning (left) and droop function (right) 8.1 offset (optional) the offset pin allows programming a positive offset (v os ) for the output voltage by connecting a resistor r offset vs. sgnd as shown in figure 7 ; this offset has to be considered in addition to the one already introduced during the production stage (v prog = vid-19 mv). offset function can be disabled shorting to sgnd the offset pin. the offset pin is internally fixed at 1.240 v ( ta b l e 5 ) a current is programmed by connecting the resistor r offset between the pin and sgnd: this current is mirrored and then properly sunk from the fb pin as shown in figure 7 . output voltage is then programmed as follow: v out i out () v prog r fb i droop i out () i offset ? [] ? ? = v prog vid 19mv ? = i droop i out () dcr rg ------------- i out ? = i offset 1.240v r offset ------------------------ = esr drop v max v min v nom response without droop response with droop comp to gnd_core (remote sense) error amplifier fb fbg r f c f vsen i droop to vcc_core (remote sense) r fb v prog v ref fbg gnd drop recovery c p i offset
L6706 voltage positioning doc id 15698 rev 2 21/47 where: offset resistor can be designed by considering the following relationship (rfb is fixed by the droop effect): offset automatically given by the dac selection differs from the offset implemented through the offset pin: the built-in feature is trimmed in production and assures 0.5% error over load and line variations figure 7. voltage positioning with positive offset 8.2 droop function this method ?recovers? part of the drop due to the output capacitor esr in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current. as shown in figure 6 , the esr drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. moreover, more and more high- performance cpus require precise load-line regulation to perform in the proper way. droop function is not then required only to optimize the output filter, but also becomes a requirement of the load. the device forces a current i droop , proportional to the read current, into the feedback r fb resistor implementing the load regulation dependence. since i droop depends on the current information, the output characteristic vs. load current is then given by (neglecting the offset voltage term): where dcr is the inductor para sitic resistance (or sense resistor when used) and i out is the output current of the system. the whole power supply can be then represented by a v out i out () v prog r fb i droop i out () 1.240v r offset ------------------------ ? ? ? = v os r fb 1.240v r offset ------------------------ ? = r offset r fb 1.240v v os ------------------ - ? = comp to gnd_core (remote sense) error amplifier fb fbg r f c f vsen i droop to vcc_core (remote sense) r fb v prog v ref fbg gnd drop recovery c p i offset 1.240v r offset offset i offset v out v prog r fb i droop ? ? v ref r fb dcr rg ------------- i out ?? ? v prog r droop i out ? ? == =
voltage positioning L6706 22/47 doc id 15698 rev 2 ?real? voltage generator with an equivalent output resistance r droop and a voltage value of v prog . r fb resistor can be also designed according to the r droop specifications as follow: r fb r droop rg dcr ------------- ? =
L6706 droop thermal compensation doc id 15698 rev 2 23/47 9 droop thermal compensation current sense element (dcr inductor) has a n on-negligible temperat ure variation. as a consequence, the sensed current is subjecte d to a measurement error that causes the regulated output voltage to vary accordingly (when droop function is implemented). to recover from this temperature related error, ntc resistor can be added into feedback compensation network, as shown in figure 8. the output voltage is then driven by the fo llowing relationship (n eglecting the offset voltage term): where r fb is the equivalent feedback resistor and it depends on the temperature through ntc resistor. considering the relationships between i droop and the i out , the output voltage results: where t is the temperature. if the inductor temperature increases the dcr inductor increases and ntc resistor decreases. as a consequence the equivalent r fb resistor decreases keeping constant the output voltage respect to temperature variation. ntc resistor must be placed as close as po ssible to the sense element (phase inductor). figure 8. ntc connections for dc load line thermal compensation v out v prog r fb i droop ? () ? = v out ti out (, ) [] v prog r fb t [] dcr t [] rg ---------------------- i out ?? ?? ?? ? = comp to gnd_core (remote sense) error amplifier fb fbg i droop to vcc_core (remote sense) v prog v ref fbg gnd drop recovery i os c p r f c f r fb ntc r fb3 r fb2 r fb1
output current monitoring (imon) L6706 24/47 doc id 15698 rev 2 10 output current monitoring (imon) the device sources from imon pin a current proportional to the load current (the sourced current is a copy of droop current). connect imon pin through a r imon resistor to remote ground (gnd core) to implement a load indicator, as shown in figure 9 . as intel vr11.1 specification required, on the imon voltage as to be added a small positive offset to avoid under-estimation of the output load (due to elements accuracy). the voltage across imon pin is given by the following formula: where: the imon pin voltage is clamped to 1.100 v max to preserve the cpu from excessive voltages as intel vr11.1 specification required. figure 9. output monitoring connection (left) and thermal compensation (right) current sense element (dcr inductor) has a n on-negligible temperat ure variation. as a consequence, the sensed current is subjecte d to a measurement error that causes the monitoring voltage to vary accordingly. to recover from this temperature related error, ntc resistor can be added into monitoring network, as shown in figure 9. the monitoring voltage is then driven by the fo llowing relationship (negle cting the offset term for simplicity): where now the r imon is the equivalent monitoring resistor and it depends on the temperature through ntc resistor. considering the relationships between i droop and the i out , the voltage results: v monitoring r imon r os ? r imon r os + ----------------------------------- i droop ? v ref r imon r imon r os + ----------------------------------- ? + = i droop dcr rg ------------- i out ? = i droop imon to gnd_core (remote sense) ntc r1 r3 r2 c imon vref = +3v3 r imon_os r imon to cpu i droop imon to gnd_core (remote sense) c imon vref = +3v3 r imon_os r imon to cpu v monitoring r imon r os ? r imon r os + ----------------------------------- i droop ? r imon r os ? r imon r os + ----------------------------------- dcr rg ------------- i out ?? ==
L6706 output current monitoring (imon) doc id 15698 rev 2 25/47 where t is the temperature. if the inductor temperature increases the dcr inductor increases and ntc resistor decreases. as a consequence the equivalent r imon resistor decreases keeping constant the monitoring voltage respect to temperature variation. ntc resistor must be placed as close as possible to the sense element (phase inductor). v monitoring ti out (, ) [] r imon tr os ? r imon tr os + --------------------------------------------- - dcr t [] rg ---------------------- i out ?? =
load transient boost technology L6706 26/47 doc id 15698 rev 2 11 load transient boost technology ltb technology? further enhances the performances of dual-edge asynchronous systems by reducing the system latencies and immedi ately turning on the phase to provide the correct amount of energy to the load. by properly designing the ltb network, as well as the ltb gain, the undershoot and the ring-back can be minimized also optimizing the output capacitors count. ltb technology? monitors the output voltage through a dedicated pin (see figure 11 ) detecting load-transients with selected dv/dt and turning-on immediately the phase. it then implements a parallel independent loop that (bypassing error amplifier (e/a) latencies) reacts to load-transients in very short time (< 150 ns). ltb technology? control loop is reported in figure 10 . figure 10. ltb technology? control loop the ltb detector is able to detect output load transients by coupling the output voltage through an r lt b - c lt b network. after detecting a load transient, the ltb ramp is reset and then compared with the comp pin level. the resulting duty-cycle pr ogrammed is then or- ed with the pwm signal by-passing the main control loop. the phase will then be turned-on and the ea latencies results bypassed as well. short ltb pin to sgnd to disable the ltb technology?: in this condition the device works as a dual-edge asynchronous pwm controller. sensitivity of the load transient detector and the gain of the ltb ramp can be programmed in order to control precisely both the undershoot and the ring-back. detector design. r lt b - c lt b is design according to the output voltage deviation dv out which is desired the controller to be sensitive as follow: ref fb comp vsen fbg r f c f r fb pwm l esr c o r o d v comp v out z f (s) z fb (s) v comp c p c fb lt b i droop monitor r lt b c lt b pwm_boost ltb ramp ltb lt detect lt detect v prog gnd drop recovery r ltbgain ltbgain r ltb dv o ut 25 a ------------------ = c ltb 1 2 r ltb f sw ?? ----------------------------------------- =
L6706 load transient boost technology doc id 15698 rev 2 27/47 gain design. through the ltbgain pin it is possible to modify the slope of the ltb ramp in order to modulate the entity of the ltb response once the lt has been detected. in fact, the response depends on the board design and its parasites requiring different actions from the controller. connect r ltbgain to sgnd using the following relati onship in order to select the default value (slope of the ltb ramp equal to 1/2 of the osc ramp slope). where f sw is the selected switching frequency (in khz). ltb technology? design tips. ? decrease r lt b to increase the syste m sensitivity making the system sensitive to smaller dv out . ? increase c lt b to increase the syste m sensitivity making the system sensitive to higher dv/dt. ? decrease r ltbgain to decrease the width of the ltb pulse reducing the system ring-back or vice versa. figure 11. ltb connection (left) and waveform (right) r ltbgain k [] 2 1240 10 3 ?? 20 fsw khz [] 200 ? 10 ------------------------------------------- - ?? ?? + ------------------------------------------------------------------- - = lt b to vcc_cor e r lt b c lt b
dynamic vid transitions L6706 28/47 doc id 15698 rev 2 12 dynamic vid transitions the device is able to manage dynamic vid code changes that allow output voltage modification during normal device operation. ovp and uvp signals are masked during every vid transition and they are re-activated after the transition finishes with a 15 s (typ) delay to prevent from false triggering due to the transition. when changing dynamically the regulated voltage (d -vid), the system needs to charge or discharge the output capacitor accordingly. this means that an extra-current i d-vid needs to be delivered, especially when increasing the output regulated voltage and it must be considered when setting the over current threshold. this current can be estimated using the following relationships: where d vout is the selected dac lsb (6.25 mv for vr11.1) and t vid is the time interval between each lsb transition (externally driven). overcoming the oc threshold during the dynamic vid causes the device to enter the constant current limitation slowing down the output voltage dv/dt also causing the failure in the d-vid test. in order to avoid this situation the device automatically increases the ocp threshold to 150% of the selected ocp threshold during every vid transition (adding an extra 15 s of delay). L6706 checks for vid code modifications (see figure 12 ) on the rising edge of an internal additional dvid-clock and waits for a confir mation on the following falling edge. once the new code is stable, on the next rising edge, the reference starts stepping up or down in lsb increments every vid-clock cycle until the new vid code is reached. during the transition, vid code changes are ignored; the device re-starts monitoring vid after the transition has finished on the next rising edge available. vid-clock frequency (f dvid ) is in the range of 1.8 mhz to assure compatibilit y with the specifications. note: if the new vid code is more than 1 lsb di fferent from the previous, the device will execute the transition stepping the reference with the dvid-clock frequency f dvid until the new code has reached: for this reason it is recommended to carefully control the vid change rate in order to carefully control the slope of the output voltage. i dvid ? c out dv ou t dt vid ----------------- - ? =
L6706 dynamic vid transitions doc id 15698 rev 2 29/47 figure 12. dynamic vid transitions t dvid x 4 step vid transition t t t vid sampled vid sampled vid sampled ref moved (1) ref moved (2) ref moved (3) ref moved (4) vid stable vid [0,7] int. reference v out t sw vid sampled vid sampled ref moved (1) ref moved (1) ref moved (1) vid sampled vid sampled 4 x 1 step vid transition t vid vid sampled vid sampled vid sampled vid sampled vid sampled vid stable vid stable vid stable ref moved (1) vid sampled vid sampled vid stable vid sampled vid sampled vid sampled t vid clock vout slope controlled by internal dvid-clock oscillator vout slope controlled by external driving circuit (t vid )
enable and disable L6706 30/47 doc id 15698 rev 2 13 enable and disable L6706 has three different supplies: vcc pin to supply the internal control logic, vccdr to supply the low side driver and boot to supply the high side driver. if the voltage at pin vcc is not above the turn on threshold specified in the electrical characteristics table (see ta b l e 5 ), the device is shut down: high-side and low-side driver keep the mosfets off to show high impedance to the load. once the device is correctly supplied, proper operation is assured and the device can be driven by the outen pin to control the power sequencing. setting the pin free, the device implements a soft-start up to the programmed voltage. shorting the pin to sgnd, it resets the device (ss_end is shorted to sgnd in this condition) from any latched condition and also disables the device keeping all the mosfet turned off to show high impedance to the load.
L6706 soft-start doc id 15698 rev 2 31/47 14 soft-start L6706 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. the device increases the reference from zero up to the programmed value and the output voltage increases accordingly with closed loop regulation. the device implements soft-start only when all the power supplies are above their own turn- on thresholds and the outen pin is set free. at the end of the digital soft-start, ss_end signal is set free. protections are active during soft-start: under voltage is enabled when the reference voltage reaches 0.6 v while over voltage is always enabled. figure 13. soft-start once L6706 receives all the correct supplies and enables, it initiates the soft-start phase with a t d1 = 1.5 ms (typ) delay. after that, the reference ramps up to v boot = 1.081 v (1.100 v - 19 mv) in t d2 according to the ssosc settings and waits for t d3 = 200 sec (typ) during which the device reads the vid lines. output voltage will then ramps up to the programmed value in t d4 with the same slope as before ( see figure 13 ). ssosc defines the frequency of an internal additional soft-sta rt-oscillator used to step the reference from zero up to th e programmed value; this oscilla tor is independent from the main oscillator whose frequency is programmed through the osc pin. the current flowing from ssosc pin before the end of soft-start is used to program the desiderated soft-start time (t ss ). after that the soft-start is finished the current flowing from ssosc pin is used to program the maximum ltb switching frequency (f limit ). in the figure 14 is shown the ssosc connection in order to select both parameter (t ss and f limit ) in independent way. in particular, it allows to precisely programming the startup time up to v boot (t d2 ) since it is a fixed voltage independent by the programmed vid. total soft-start time dependence on the programmed vid results (see figure 15 ). note: if during t d3 the programmed vid selects an output voltage lower than v boot , the output voltage will ramp to the progra mmed voltage starting from v boot . outen ss_end v out t t t t d1 t d2 t d3 t d4 t ss ovp t d5
soft-start L6706 32/47 doc id 15698 rev 2 figure 14. ssosc connection where t ss is the time spent to reach the programmed voltage v ss and r ssosc the resistor connected between ssosc and ssend (through a signal diode) in k . figure 15. soft-start time (t ss ) when using r ssosc , diode versus ssend use the following relationship to select the maximum ltb switching frequency: where f limit has to be higher than the f sw switching frequency. ssosc ss_end r ssosc d q r pull-up (1k) v pull-up (1.2v) to ssend logic r b (10k) r flimit soft start time and flimit selected in indipendent way. r flim_ss soft start time depends on selected flimit. r ssosc k [] t d2 s [] 40 10 3 ? 1.24 v diode v [] ? 1.24 ---------------------------------------------- - ?? ? = t ss s [] 200 s [] r ssosc k [] 40 10 3 ? ? ----------------------------------- 1.24 1.24 v diode v [] ? ---------------------------------------------- - v ss v boot ------------------ ?? if v ss v boot > () r ssosc k [] 40 10 3 ? ? ----------------------------------- 1.24 1.24 v diode v [] ? ---------------------------------------------- - 1 v ss v boot ------------------ + ?? if v ss v boot < () ? ? ? ? ? ? ? + = r flimit k [] 2.11 10 4 ? f limit khz [] --------------------------------- 1.24 v ce bjt v [] ? 1.24 ---------------------------------------------- - ? =
L6706 soft-start doc id 15698 rev 2 33/47 note: connecting ssosc pin to sgnd through only the r flim_ss resistor (blue one network in figure 14 ), the soft-start time depends on the f limit selected. in this case use the following relationship to select f limit and as a consequence the soft- start time: figure 16. soft-start time (t ss ) vs f limit when using r flim_ss resistor versus sgnd 14.1 low-side-less startup in order to avoid any kind of negative undershoot on the load side during startup, L6706 performs a special sequence in enabling ls driver to switch: during the soft-start phase, the ls driver results disabled (ls = off) until the hs starts to switch. this avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output (see figure 17 ). this particular feature of the device masks the ls turn-on only from the control loop point of view: protections are still allowed to turn-on t he ls mosfet in case of over voltage if needed. figure 17. low-side-less startup comparison.with ls-less startup r flim ss ? k [] 2.11 10 4 ? f limit khz [] --------------------------------- = t d2 s [] 5.275 10 5 ? f limit khz [] --------------------------------- = v out v out lgate lgate without ls-less startup with ls-less startup
output voltage monitor and protections L6706 34/47 doc id 15698 rev 2 15 output voltage monitor and protections L6706 monitors through pin vsen the regulate d voltage in order to manage the ovp and uvp conditions. protections are active also during soft-start ( see ?soft-start? section ) while they are masked during d-vid transitions with an additional 67s delay after the transition has finished to avoid false triggering. 15.1 undervoltage if the output voltage monitored by vsen dr ops more than 600 mv (typ) below the programmed reference for more than one clock period, the L6706: ? permanently turns off the mosfets ? drives the osc/ fault pin high (3.3 v typ). ? power supply or outen pin cycling is required to restart operations. 15.2 preliminary overvoltage to provide a protection wh ile vcc is below the uvlo vcc threshold is fundamental to avoid damage to the cpu in case of fa iled hs mosfets. in fact, sinc e the device is supplied from the 12 v bus, it is basically ?blind? for any voltage below the turn-on threshold (uvlo vcc ). in order to give full protection to the load, a preliminary-ovp protection is provided while vcc is within uvlo vcc and uvlo pre-ovp . this protection turns-on the lo w side mosfets as long as th e vsen pin voltage is greater than 1.800 v with a 350 mv hysteresis. when set, the protection drives the ls mosfet with a gate-to-source voltage depending on the voltage applied to vcc. this protection depends also on the outen pin status as detailed in figure 18 . a simple way to provide protection to the output in all conditions when the device is off (then avoiding the unprotected red region in figure 18-left ) consists in supplying the controller through the 5 v sb bus as shown in figure 18-right : 5v sb is always present before +12 v and, in case of hs short, the ls mosfet is driven with 5v assuring a reliable protection of the load. figure 18. output voltage protections and typical principle connections v cc uvlo ovp uvlo vcc preliminary ovp enabled vsen monitored no protection provided (outen = 1) programmable ovp vsen monitored (outen = 0) preliminary ovp vsen monitored vcc vccdr +12v +5v sb 10 2.2 bat54c 1 f 1 f
L6706 output voltage monitor and protections doc id 15698 rev 2 35/47 15.3 over voltage and programmable ovp once vcc crosses the turn-on threshold and the device is enabled (outen = 1), L6706 provides an over voltage prot ection: when the voltage sensed by vsen overcomes the ovp threshold (ovp th ), the controller: ? permanently turns off the high-side mosfets. ? permanently turns on the low-side mosfet in order to protect the load. ? drives the osc/ fault pin high (3.3 v typ). ? power supply or outen pin cycling is required to restart operations. the ovp threshold can be also programmed through the ovp pin: leaving the pin floating, it is internally pulled-up and the ovp threshold is set to vid + 175 mv (typ). connecting the ovp pin to sgnd through a resistor r ovp , the ovp threshold becomes the voltage present at the pin. since the ovp pin sources a constant i ovp = 20 a (min) current (see ta b l e 5 ), the programmed voltage becomes: filter ovp pin with 100 pf (max) vs. sgnd. over voltage protections is always active during the soft-start, as shown in the following picture: figure 19. ovp threshold during soft-start for tracking (left) and fixed (right) mode 15.4 overcurrent protection the device limits the peak the inductor current entering in constant current until setting uvp as below explained. the over current threshold has to be programmed, by designing the r ocset resistors as shown in the figure 20 , to a safe value, in order to be sure that the device doesn't enter table 8. over voltage protection threshold ovp pin thresholds ovp threshold floating tracking ovp th = vid + 175 mv (typ) r ovp to sgnd fixed ovp th = r ovp * 20 a (min) ovp th r ovp 20 amin ) () ? = r ovp ovp th 20 amin ) () ---------------------------------- = ? outen ss_end v out t t t 1.240v t ovp th vid+150mv(min) outen ss_end v out t t t r ovp * 22ua(min) t ovp th
output voltage monitor and protections L6706 36/47 doc id 15698 rev 2 ocp during normal operation of the device. this value must take into consideration also the extra current needed during the dynamic vid transition i d-vid (see section 12: dynamic vid transitions for details): the device detects an over current when the i info overcome the threshold i octh externally programmable through ocset pin. where il is the inductor ripple current (peak-to-peak). since the device always senses the current across the inductor, the i octh crossing will happen during the hs conduction time: as a co nsequence of ocp detection, the device will turn off the hs mosfet and turns on the lsmosfet until i info re-cross the threshold or until the next clock cycle. this implies th at the device limits the peak of the inductor current. in any case, the inductor current won't overcome the i ocp value and this will represent the maximum peak value to consider in the oc design. the device works in constant-current, and the output voltage decreases as the load increase, until the output voltage reaches the uvp threshold. when this threshold is crossed, mosfets are turned off and the device stops working. cycle the power supply or the outen pin to restart operation. figure 20. overcurrent protection connection note: in order to avoid the ocp intervention during the dvid, the device automatically increases the ocp threshold to 150% of the selected ocp threshold during every vid transition (adding an extra 15 s of delay). since the device reads the current information across inductor dcr, the process spread and temperature variations of these sensing elements has to be considered. also the programmable threshold spread (i octh current spread as a consequence of v ocset spread, see ta bl e 5 ) has to be considered for the r ocset design: iout ocp iout max i dvid ? + > i octh v ocset r ocset --------------------- - 1.260 typ () r ocset ---------------------------- == i info ocp dcr rg ------------- i out ocp il 2 -------- - + ?? ?? ? = r ocset ocset v ocset =1.260v ( typ) i octh r ocset v ocset min () dcr max ) () rg ----------------------------------- i out ocp () il 2 -------- - + ?? ?? ? 77 a + ----------------------------------------------------------------------------------------------------------------------- =
L6706 output voltage monitor and protections doc id 15698 rev 2 37/47 15.5 feedback disconnection L6706 allows to protect the load from dangerous over voltage also in case of feedback disconnection. the device is able to recogniz e both fb pin and fbg pin disconnections, as shown in the figure 21 . when vsen pin is more than 500 mv higher then vprog, the device recognize a fbg disconnections. viceversa, when cs- is more than 700 mv higher then vsen, the device recognize a fb disconnection. in both of the previous condition the device stops switching with the mosfets permanently off and drives high the osc/fault pin. th e condition is latched until vcc or outen cycled. figure 21. feedback disconnection comp to gnd_core (remote sense) error amplifier fb fbg r f c f vsen i dr oop to vcc_core (remote sense) r fb v prog v ref fbg gnd drop recovery c p l dcr phase v out cs+ cs- r c rg fb disconnected 700mv fbg disconnected 500mv i os
oscillator L6706 38/47 doc id 15698 rev 2 16 oscillator the internal oscillator generates the tria ngular waveform for the pwm charging and discharging with a constant current an internal capacitor. the current delivered to the oscillator is typically 25 a (corresponding to the free running frequency f sw = 200 khz) and it may be varied using an external resistor (r osc ) connected between the osc/fault pin and sgnd or vcc (or a fixed voltage greater than 1.24 v). since the osc/fault pin is fixed at 1.240 v, the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 10 khz/ a. in particular connecting r osc to sgnd the frequency is increased (current is sunk from the pin), while connecting r osc to vcc = 12 v the frequency is reduced (current is forced into the pin), according the following relationships: r osc vs. sgnd r osc vs. +12v maximum programmable switching frequency must be limited to 1 mhz to avoid minimum ton limitation. anyway, device power dissipation must be checked prior to design high switching frequency systems. figure 22. r osc vs. switching frequency f sw 200 khz () 1.240v r osc k () ---------------------------- 9.1 khz a ---------- - ? + 200 khz () 11.284 10 3 ? r osc k () ------------------------------- - r osc k () ? + 11.284 10 3 ? f sw khz () 200 khz () ? ----------------------------------------------------------- - == = k [] f sw 200 khz () 12v 1.240v ? r osc k () ----------------------------------- - 9.1 khz a ---------- - ? ? 200 khz () 9.7916 10 4 ? r osc k () ------------------------------- - ? r osc k () ? 9.7916 10 4 ? 200 khz () f sw khz () ? ----------------------------------------------------------- - == = k []
L6706 driver section doc id 15698 rev 2 39/47 17 driver section the integrated high-current driver allow using different types of power mos (also multiple mos to reduce the equivalent r ds(on) ), maintaining fast switching transition. the driver for the high-side mosfets use boot pin for supply and phase pin for return. the driver for the low-side mosfets use vc cdr pin for supply and pgnd pin for return. a minimum voltage at vccdr pin is required to start operations of the device. the controller embodies a sophisticated anti-s hoot-through system to minimize low side body diode conduction time maintaining good ef ficiency saving the use of schottky diodes: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2 v, the low-side mosfet gate drive is suddenly applied. when the low- side mosfet turns off, the voltage at lgate pin is sensed. when it drops below 1v, the high-side mosfet gate drive is suddenly applied. if the current flowing in the in ductor is negative, the source of high-side mosfet will never drop. to allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet doesn't drop, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. the boot and vccdr pin are separated from ic's power supply (vcc pin) as well as signal ground (sgnd pin) and power ground (pgnd pin) in order to maximize the switching noise immunity.
system control loop compensation L6706 40/47 doc id 15698 rev 2 18 system control loop compensation the control loop is an average current mode control loop (see figure 5 ): the output voltage is equal to the reference programmed by vid minus the droop function terms. the system control loop is reported in figure 24 . the current information i droop sourced by the fb pin flows into r fb implementing the dependence of the output voltage from the read current. figure 23. main control loop the control loop gain results (obtained opening the loop after the comp pin): where: dcr is the inductor parasitic resistance; is the equivalent output resistance determined by the droop function; z p (s) is the impedance resulting by the parallel of the output capacitor (and its esr) and the applied load r o ; z f (s) is the compensation network impedance; z l (s) is the inductor impedance; a (s) is the error amplifier gain; is the pwm transfer function where v osc is the oscillator ramp amplitude and has a typical value of 1.5 v. removing the dependence from the error amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results: the system control loop gain (see figure 23 ) is designed in order to obtain a high dc gain to minimize static error and to cross the 0db axes with a constant -20 db/dec slope with the l pwm v ref error amplifier comp fb z f (s) z fb (s) i droop c out r out g loop s () pwm z f s () r droop z p s () + () ?? z p s () z l s () + [] z f s () as () -------------- 1 1 as () ----------- - + ?? ?? r fb ? + ? ------------------------------------------------------------------------------------------------------------------- ? = r droop dcr rg ------------- r f b ? = p wm 3 5 -- - v in v os c ----------------- - - ? = g loop s () 3 5 --- - v in v osc --------------------- - z f s () r fb --------------- r o r droop + r o r l + ------------------------------------------- - 1sc o r droop //r o esr + () ?? + s 2 c o l ?? s l r o -------- - c o esr ? c o r l ? ++ 1 + ? + ------------------------------------------------------------------------------------------------------------------------------- - ??? ? ? =
L6706 system control loop compensation doc id 15698 rev 2 41/47 desired crossover frequency t . neglecting the effect of z f (s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (lc filter resonance lc ) and the zero ( esr ) is fixed by esr and the droop resistance. figure 24. equivalent control loop block diagram (left) and bode diagram (right) to obtain the desired shape an r f - c f series network is considered for the z f (s) implementation. a zero at f = 1/r f c f is then introduced together with an integrator. this integrator minimizes the static error while placing the zero f in correspondence with the l- c resonance assures a simple -20 db/dec shape of the gain. in fact, considering the usual value for the output filter, the lc resonance results to be at frequency lower than the above reported zero. compensation network can be simply designed placing f = lc and imposing the cross- over frequency t as desired obtaining (always considering that t might be not higher than 1/10th of the switching frequency f sw ): moreover, it is suggested to filter the high fr equency ripple on the comp pin adding also a capacitor between comp pin and fb pin (it does not change the system bandwidth): vref fb comp vsen fbg r f c f r fb pwm l esr c o r o d v out v out z f (s) z fb (s) i droop db z f (s) g loop (s) k lc = f esr t r f [db] c p r f r fb v osc ? v in --------------------------------- - 5 3 -- - t l r droop esr + () ---------------------------------------------- - ?? ? = c f c o l ? r f ------------------- - = c p 1 2 r ? f f sw ?? -------------------------------------- - =
power dissipation L6706 42/47 doc id 15698 rev 2 19 power dissipation L6706 embeds high current mosfet drivers for both high side and low side mosfets: it is then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. exposed pad needs to be soldered to the pcb power ground plane through several vias in order to facilitate the heat dissipation. two main terms contribute in the device power dissipation: bias power and drivers' power. the first one (p dc ) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply hs and ls drivers with the same vcc of the device): drivers' power is the power needed by the driver to continuously switch on and off the external mosfets; it is a function of the switching frequency and total gate charge of the selected mosfets. it can be quantified considering that the total power p sw dissipated to switch the mosfets (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic mosfet re sistance and intrinsic driver resistance. this last term is the important one to be determined to calculate the device power dissipation. the total power dissipated to switch the mosfets results: external gate resistors helps the device to dissipate the switching power since the same power p sw will be shared between the internal driv er impedance and the external resistor resulting in a general cooling of the device. when driving multip le mosfets in parallel, it is suggested to use one gate resistor for each mosfet. figure 25. L6706 dissipated power (quiescent + switching) p dc v cc i cc i ccdr i boot ++ () ? = p sw f sw q ghs v boot ? q gls v ccdr ? + () ? =
L6706 layout guidelines doc id 15698 rev 2 43/47 20 layout guidelines since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. a good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection be tween signal and power ground can optimize the performance of the control loops. two kind of critical components and connections have to be considered when layouting a vrm based on L6706: power components and connections and small signal components connections. 20.1 power components and connections these are the components and connections where switching and high continuous current flows from the input to the load. the first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. to minimize noise and voltage sp ikes (emi and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. the critical components, i.e. the power transistors, must be close one to the other. the use of multi-layer printed circuit board is recommended. figure 26 shows the details of the power connections involved and the current loops. the input capacitance (c in ), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. low esr and esl capacitors are preferred, mlcc are suggested to be connected near the hs drain. use proper vias number when power traces have to move between different planes on the pcb in order to reduce both parasitic resistance and inductance. moreover, reproducing the same high-current trace on more than one pcb layer will reduce the parasitic resistance associated to that connection. connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. gate traces must be sized according to the driver rms current delivered to the power mosfet. the device robustness allows managing applications with the power section far from the controller without losing performances. external gate resistors help the device to dissipate power resulting in a general cooling of the device. when driving multiple mosfets in parallel, it is suggested to use one resistor for each mosfet. 20.2 small signal components and connections these are small signal components and connecti ons to critical nodes of the application as well as bypass capacitors fo r the device supply (see figure 26 ). locate the bypass capacitor (vcc and bootstrap capacitor) close to the de vice and refer sensible components such as frequency set-up resistor r osc , over current resistor r ocset . star grounding is suggested: connect sgnd to pgnd plane in a single point to avoid that drops due to the high current delivered causes errors in the device behavior. remote sensing connection must be routed as para llel nets from the fb g/vsen pins to the load in order to avoid the pick-up of any common mode noise. connecting these pins in
layout guidelines L6706 44/47 doc id 15698 rev 2 points far from the load will cause a non-optimum load regulation, in creasing output tolerance. locate current reading components close to the device. the pcb traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. it's also important to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. small filtering capacitor can be added, near the controller, between v out and sgnd, on the cs- line to allow higher layout flexibility. power connections and related connections layout. figure 26. power connections and related connections layout note: boot capacitor extra charge. systems that do not use schottky diodes might show big negative spikes on the phase pin. this spike can be limited as well as the positive spike but has an additional consequence: it causes the boo tstrap capacitor to be over-charged. this extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device failures. it is then suggested in this cases to limit this extra-charge by adding a small resistor in series to the boot diode (see figure 26 ) and by using standard and low- capacitive diodes. 20.3 embedding L6706 - based vr when embedding the vrd into the application, additional care must be taken since the whole vrd is a switching dc/dc regulator and th e most common system in which it has to work is a digital system such as mb or similar. in fact, latest mb has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the vrd can affect data integrity if not following additional layout guidelines. few easy points must be considered mainly w hen routing traces in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces): keep safe guarding distance between high current switching vrd traces and data buses, especially if high-speed data bus to minimize noise coupling. keep safe guard distance or filter properly when routing bias traces fo r i/o sub-systems that must walk near the vrd. possible causes of noise can be located in the phase connection, mosfet gate drive and input voltage path (from input bulk capacitors and hs drain). also pgnd connection must be considered if not insisting on a power ground plane. these connections must be carefully kept far away from noise-sensitive data bus. since the generated noise is mainly due to the switching activity of the vrm, noise emissions depend on how fast the current switches. to reduce noise emission levels, it is also possib le, in addition to the previous guidelines, to reduce the current slope by properly tuning the hs gate re sistor and the phase snubber network. l c in v in ugate phase lgate pgnd load boot phase vcc sgnd +vcc c boot l c in v in load to limit c boot extra-charge
L6706 package mechanical data doc id 15698 rev 2 45/47 21 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 27. vfqfpn-40 package dimensions table 9. vfqfpn-40 mechanical data dim. mm inch min. typ. max. min. typ. max. a 0.800 0.900 1.000 0.031 0.035 0.039 a1 0.020 0.050 0.0008 0.0019 b 0.180 0.250 0.300 0.007 0.009 0.012 d 5.900 6.000 6.100 0.232 0.236 0.240 d2 3.950 4.100 4.200 0.155 0.161 0.165 e 5.900 6.000 6.100 0.232 0.236 e 0.240 e2 3.950 4.100 4.200 0.155 0.161 0.165 e 0.500 0.020 l 0.300 0.400 0.500 id 0.012 0.015 0.018 ddd 0.080 0.003 ddd
revision history L6706 46/47 doc id 15698 rev 2 22 revision history table 10. document revision history date revision changes 26-may-2009 1 first release 20-jan-2010 2 updated table 2 on page 6 , table4 on page10 , chapter 10 on page 24 , figure 9 on page 24 and chapter 16 on page 38
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